1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a semiconductor device where a low voltage transistor that operates at a low operating voltage and a high voltage transistor that operates at a higher operating voltage than the low operating voltage are formed on the same semiconductor substrate.
2. Description of the Related Art
In a low voltage transistor that operates at a relatively low operating voltage (also called a low withstand voltage transistor), it is necessary to lower the resistance of the source/drain regions in order to improve the operating speed of the transistor. And in order to lower the resistance of the source/drain regions, it is necessary to shorten the length of the low concentration diffusion region of the transistor.
In a high voltage transistor that operates at a higher operating voltage than the low operating voltage (also called a high withstand voltage transistor), it is necessary to alleviate the electric field that arises in the end portion of the drain region in order to control deterioration of hot-carrier transistor characteristics. And in order to alleviate the electric field that arises in the end portion of the drain region, it is necessary to lengthen the length of the low concentration diffusion region of the transistor.
The length of the low concentration diffusion region of a transistor is dependent on the width of a side wall spacer formed on a side wall of a gate electrode. Consequently, in a semiconductor device where a low voltage transistor and a high voltage transistor are formed on the same semiconductor substrate, how a side wall spacer having a width corresponding to the characteristics of each transistor can be precisely formed is becoming important.
Japanese Patent Application Publication (JP-A) No. 2003-60067 discloses relatively shortening the width of an LDD region by forming a single layer spacer on the side wall of a gate electrode of a low voltage transistor. JP-A 2003-60067 also discloses relatively enlarging the width of the LDD region and alleviating the electric field at the drain end portion by forming a two layer spacer on the side wall of a gate electrode of a high voltage transistor.
Further, in recent years, where there is a demand for even higher speed operation of semiconductor devices, it has become common to apply the silicide process, where Ti silicide or Co silicide is formed on the gate electrode and the source/drain regions of a transistor, to semiconductor devices to lower the resistance of the gate electrode and the source/drain regions of the transistor. It will be noted that JP-A No. 2003-60067 also discloses that the silicide process is applied to a semiconductor device.
However, the present inventors have discovered that there is room for improvement in the above semiconductor devices in terms of the following points.
In a semiconductor device to which the silicide process is applied, it is necessary for the top surface of the gate electrode of a transistor configured by PolySi to be exposed. This is because it is necessary for Co to be directly formed on Si or PolySi in order for silicidation of Co to occur.
In FIG. 1, the relationship between the film thickness of a side wall spacer film and the dimension (width) of a side wall spacer is shown. As shown in FIG. 1, there is a tendency for the spacer dimension to not increase linearly with respect to an increase in the film thickness of the spacer film and for the amount of increase in the spacer dimension to decrease together with an increase in the spacer film thickness. As shown in FIG. 2, it will be understood that there is a tendency for the angle represented by symbol “a” to become gentler in accompaniment with an increase in the film thickness of the spacer film.
In FIG. 3 and FIG. 4, the mechanism of reduction of the spacer dimension increase amount accompanying the spacer film thickness increase is shown. As shown in (A) of FIG. 3, when the spacer film shape in the vicinity of the gate electrode after formation of the spacer film is close to a vertical shape, then the spacer shown in (B) of FIG. 3 is formed without the spacer dimension changing during spacer etching. In contrast, as shown in (A) of FIG. 4, when the spacer film shape in the vicinity of the gate electrode after formation of the spacer film is gentle, then as shown in (B) of FIG. 4, a reduction of the spacer dimension occurs in accompaniment with etching. As a result, it becomes difficult to ensure a spacer width that sufficiently satisfies device characteristics.
Further, because the spacer width changes due to the amount of etching, it is conceivable to deposit a hard mask or the like on the top surface of the gate electrode and substantially increase the film thickness of the gate electrode formation portion in order to stably increase the spacer width. However, in a semiconductor device to which the silicide process is applied, it is necessary for the top surface of a gate electrode configured by PolySi to be exposed during Co film formation. That is, when a hard mask is used, the step of removing the hard mask becomes necessary during Co film formation. Thus, from the standpoint of optimizing steps, it is not preferable to use a hard mask just for the purpose of stably increasing the spacer width.
As described above, in a case where the silicide process is applied when manufacturing a semiconductor device where a low voltage transistor and a high voltage transistor are formed on the same semiconductor substrate, it is necessary for the top surface of the gate electrode to be exposed after spacer etching. Thus, there have been points for improvement in that it has been impossible to increase the film thickness of the gate electrode formation portion using a hard mask or the like and it has been difficult to stably form a spacer width that sufficiently satisfies device characteristics.